1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device that can output a mode signal set in a mode register to outside.
2. Description of Related Art
Various types of operation modes are prepared in many semiconductor memory devices. A specific operation mode can be selected among the prepared operation modes by setting a predetermined mode signal in a mode register.
A mode signal set in a mode register can be read by issuing a mode register read command (MRR command) from outside (see Japanese Patent Application Laid-Open No. 9-259582). However, in conventional semiconductor memory devices, differently from ordinary data reading, the mode signal read from the mode register is supplied onto a signal path in a data input/output circuit in a manner in which the mode signal intervenes in the data input/output circuit. Therefore, when the mode register read command is issued right after a read command, read data flowing in the data input/output circuit collides with the mode signal read from the mode register.
For this reason, it is necessary to wait for a predetermined time period after issuing the read command so as to prevent such data collision. This means that it is necessary to handle the mode register read command as an exception in regard of minimum issuance intervals of issuing continuous commands (CAS to CAS delay). This leads to a problem that controller-side control is complicated.
Therefore, under these circumstances, it has been desired to provide a semiconductor memory device capable of preventing collision of read data with a mode signal in a data input/output circuit, even when a read command and a mode register read command are continuously issued at minimum issuance intervals.